The present invention relates to an electronic device having a seal ring formed to surround a chip region and a mechanism for protecting the seal ring and to a method for fabricating the same.
An electronic device such as a semiconductor device is typically formed by arranging a large number of IC circuits each composed of a plurality of elements and having a specified function as a matrix on a semiconductor wafer made of, e.g., silicon or the like.
A large number of chip regions arranged in the wafer are separated from each other by scribe regions (scribe lines) provided in a grid-like configuration. After the large number of chip regions are formed in a single wafer through a semiconductor fabrication process, the wafer is diced into individual chips along the scribe regions so that semiconductor devices are formed.
When the wafer is diced to be separated into the individual chips, however, the portions of the chip regions which are adjacent to the scribe lines receive mechanical impact, which may cause local cracks or chippings in the cross sections of the individual chips, i.e., semiconductor devices into which the wafer has been separated.
As a solution to the problem, Japanese Laid-Open Patent Publication No. 2001-23937 proposes a technology which provides a seal ring as a ring-shaped protective wall around each of the chip regions to prevent the propagation of a crack in the chip region during dicing.
FIG. 32 shows a cross-sectional structure of a conventional semiconductor device (that has been embedded in a wafer) having a seal ring.
As shown in FIG. 32, a seal ring 4 extending through the multilayer structure and continuously surrounding the chip region 2 is formed in the portion of the multilayer structure consisting of the plurality of interlayer insulating films 5 to 10 which is located in the peripheral portion of the chip region 2. The seal ring 4 is formed by alternately using a mask for wire formation and a mask for via formation, as shown in, e.g., Japanese Laid-Open Patent Publication No. 2001-23937. Specifically, the seal ring 4 is composed of: a conductive layer 30 formed in the substrate 1, a seal via 31 formed in the interlayer insulating film 5 and connecting to the conductive layer 30; a seal wire 32 formed in the interlayer insulating film 6 and connecting to the seal via 31; a seal via 33 formed in the interlayer insulating film 7 and connecting to the seal wire 32; a seal wire 34 formed in the interlayer insulating film 8 and connecting to the seal via 33; a seal via 35 formed in the interlayer insulating film 9 and connecting to the seal wire 34; and a seal wire 36 formed in the interlayer insulating film 10 and connecting to the seal via 35. In the present application, the portions of the seal ring formed by using the mask for wire formation will be termed seal wires and the portions of the seal ring formed by using the mask for via formation will be termed seal vias.
As also shown in FIG. 32, a passivation film 11 is further provided over the multilayer structure consisting of the plurality of interlayer insulating films 5 to 10 and provided with the wires (22, 24, and 26) and with the vias (21, 23, and 25). The passivation film 11 has an opening formed over the wire 26 and a pad 27 connecting to the wire 26 is formed in the opening.